MC 68030 : The second generation 32 - bit microprocessor

The MC68030 is a virtual memory microprocessor based on an MC68020 core with additional enhanced performance features. Increased internal parallelism is provided by multiple internal data buses and address buses, and a versatile bus controller that supports synchronous burst cycle accesses in order to maximize performance with paged mode, nibble mode, and static column DRAM technology, or even external SRAM caches. A 256-byte on-chip instruction cache in addition to a 256-byte on-chip data cache improves data flow to the execution unit and further boosts performance regardless of the actual external memory configuration. On-chip paged memory management reduces the minimum physical bus cycle time to two clocks, and provides zero translation time to any bus cycle. The paged memory management structure can be enabled/disabled by software for applications not requiring the memory management feature. The rich instruction set and addressing modes of the MC68020 have been maintained allowing a clear migration path for M68000 systems.